1. Technical Field
The invention relates in general to a semiconductor structure and a semiconductor circuit.
2. Background
The BICMOS-DMOS (BCD) process has been widely used in modern smart power applications. Smart Power ICs usually use Lateral Diffusion MOS transistors (LDMOS) for switching because of the characteristic of low on-state resistance of the LDMOS. Due to the characteristic of low on-state resistance, the LDMOS device has electrostatic discharge (ESD) currents occurred mainly in the surface or the drain edge during an ESD event of the LDMOS device. Consequently, the surface junction region of the LDMOS device will be destructed due to high currents and high electric field. The ESD protection performance of the LDMOS device usually depends on the total width and the surface or the lateral rules thereof. However, the surface or the lateral rules can't be increased to improve the ESD protection performance based on electrical requirements of the low on-state resistance. Therefore, how to design an ESD protection structure with better performance has become a main issue currently.